In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations for optimizing their particular memories, many such systems now include an internal state machine for controlling the detailed operation of the memory system. The internal state machine controls the primary operations of the memory system, including reading, programming and erasing operations. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the state machine.
The operating characteristics of integrated circuit memory systems, especially large capacity memory systems, depend upon many factors. These factors include process variations during the fabrication of the memory system. Thus, two memory systems which are nominally the same, may nevertheless have different operating characteristics which are not ascertainable until the memory systems are actually fabricated. The internal state machine of the memory system needs to be implemented in a manner which takes into account these variations in memory characteristics, while providing a memory system which meets certain performance specifications. Thus, the internal state machine cannot be optimized for a particular set of memory system characteristics, but must be implemented in a manner which provides adequate operation over a range of memory characteristics.
Once an integrated memory system has been fabricated, it is possible to characterize the system, but it is no longer possible to alter the manner in which the state machine carries out the memory system sub-operations. As will be explained in greater detail, the present invention permits the operation of the internal state machine to be altered after fabrication of the memory system. This means that operation of the state machine, particularly with respect to the sub-operations, can be optimized to take into account the actual characteristics of the memory system. By altering the operation of the internal state machine, the sub-operations themselves can be characterized and the impact of the sub-operations on the overall process flow can be determined.
FIG. 1 is a functional block diagram of a conventional flash memory system 1. The core of memory system 1 is an array 12 of flash memory cells. The individual cells in array 12 are arranged in rows and columns, with there being, for example, a total of 256K eight bit words in array 12. The individual memory cells (not shown) are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 13. Nine of the eighteen address bits are used by X decoder 14 to select the row of array 12 in which a desired memory cell is located and the remaining nine bits are used by Y decoder 16 to select the appropriate column of array 12 in which the desired cell is located.
Memory system 1 contains an internal state machine (ISM) 20 which controls the data processing operations and sub-operations performed on memory array 12. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array 12. In addition, internal state machine 20 controls such operations as reading or clearing status register 26, identifying memory system 1 in response to an identification command, and suspending an erase operation. State machine 20 functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system 1.
For example, if memory cell array 12 is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin OE to be inactive (high), and the chip enable CE and write enable WE pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins 15 (DQ0-DQ7), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command D0H (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation so as to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins 15 are transferred to data input buffer 22 and then to command execution logic unit 24. Command execution logic unit 24 receives and interprets the commands used to instruct state machine 20 to perform the steps required for erasing array 12 or carrying out another desired operation. Once the desired operation sequence is completed, state machine 20 updates 8 bit status register 26. The contents of status register 26 is transferred to data output buffer 28, which makes the contents available on data I/O pins 15 of memory system 1. Status register 26 permits the external processor to monitor certain aspects of the status of state machine 20 during memory array write and erase operations. The external processor periodically polls data I/O pins 15 to read the contents of status register 26 in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
As noted, the contents of status register 26 provides information to a user of memory system 1 concerning the internal operation of the memory system. This information includes the status (ready or busy) of state machine 20, whether an erase or write operation has been successful, whether an erase operation has been suspended, and whether the write/erase supply voltage (V.sub.PP) is present.
In programming or erasing the memory elements contained in array 12, memory system 1 accesses each memory element and evaluates the margins (the voltage differential between the threshold voltage of the memory cells and ground level) that the element has after the operation. The system then decides whether the element needs to be reprogrammed or erased further to achieve a desired operational margin. This treatment of the memory elements requires control logic that causes the memory system to be very complicated.
The memory array needs to be programmed first in a pre-programming cycle before it can be erased. This is to avoid over-erasing the bits in some memory elements to a negative threshold voltage, thereby rendering the memory inoperative. During this cycle of pre-programming, the memory system needs to check to see if the bits are programmed to a sufficient level. This is accomplished by a programming verification cycle that uses a different evaluation procedure than a regular read operation would use. After successful completion of the pre-programming cycle, a high voltage erase operation is executed. After the erase operation is completed, some memory systems go through an operation to tighten the distribution (reduce the variance) of memory element threshold voltages for ease of manufacturing. After this procedure, the memory system may perform a reverify operation to determine if the data in the memory array has remained undisturbed.
FIG. 2 is a state diagram showing the process flow (sub-operations) of a typical memory system of the type shown in FIG. 1 during the pre-programming, high voltage erase, and distribution adjustment stages which occur during a complete erase operation. The complete erase operation starts with a pre-program cycle 200. This sub-operation programs all the elements in the memory array to a logic 0 value to make sure that the erase process starts from a known cell threshold voltage level. This part of the complete erase operation is used to reduce the possibility of over erasure of some of the memory elements during the later steps.
The pre-program cycle begins with an operation which increments the address of the memory cell which is to be pre-programmed 202. This is done because the pre-programming operation is executed on a cell by cell basis. This step is followed by a high voltage level set-up stage 204 which prepares the system for application of the high voltage levels (typically about 12 volts is applied to the gate of each memory cell and 6 volts to the drain) used for programming a cell. The high voltage level used for writing to (programming) the cell is then applied in stage 206.
The appropriate voltage levels for executing the data verification sequence (reading the data programmed in the cell and comparing it to a desired value) are applied to the appropriate circuitry at stage 208. This is followed by a program verification stage 210 which verifies that the programmed cell has sufficient margin. This is typically accomplished by comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage. If the verification operation was not successful, steps 204, 206, 208, and 210 are repeated. Once the verification stage for a particular memory cell is successfully completed, it is followed by a program clean up stage 212.
Program clean up stage 212 conditions all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. This concludes the pre-programming cycle for a given memory cell. The address of the cell to be operated on is then incremented at stage 202 and the process repeats itself until the last cell in a memory block to be erased is programmed. At this time, the incremented address will point to the first address location in the block, which is the first address for the next operation. When this occurs, all of the memory cells have been successfully pre-programmed and control is passed to the high voltage erase cycle 220.
In the erase cycle, the memory system performs a block erase operation on all of the cells contained in a block of memory. The first stage in the cycle is a high voltage level set-up stage 222 which prepares the memory block for application of the high voltage pulse(es) used for erasing the cells. This is followed by a high voltage stage 224 in which a short, high voltage pulse is applied to erase all of the memory cells in the block of cells. This is followed by a set-up verify stage 226 which applies the appropriate voltage levels for the data verification stage to the corresponding circuits. The next stage is an erase verify stage 228 which verifies that the erase operation was successfully carried out on each cell in the block. This is accomplished by accessing the cells, address by address and comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage.
If the erase operation was not successfully carried out (a cell was not erased to the proper margin), control is passed back to the high voltage level set-up stage 222 and the high voltage cycle is carried out again to erase the entire block of cells. If the erase operation was successful for the cell under consideration, the address of the memory cell is incremented 230 and the next cell is tested for verification of the erase operation. Thus, if the maximum address of the cells in the block of memory has not been reached, erase verify stage 228 is carried out on the next memory cell in the block. If the maximum address for cells in the block has been reached (meaning that all the cells in the memory block have been successfully erased), control is passed to the distribution adjustment stage 240.
The distribution adjustment sub-operation 240 is used to tighten the distribution (reduce the variance) of the threshold voltages of the erased memory elements. This is done by applying high voltages (i.e., 12 volts) to the gates of all the memory cells in the memory block, with the memory cell drains floating and the sources at ground potential.
The distribution adjustment cycle begins with a high voltage set-up stage 242, which is followed by a high voltage stage 244 in which the voltages used to perform the adjustment sub-operation are applied. This is followed by set-up verification 246 stage which applies the appropriate voltage levels to the corresponding circuits, and erase verification 248 stage which acts to insure that all of the erased cells are still in an erased state. If the erase verification procedure fails, a final erase 249 stage may be executed. In the final erase stage, a short erase pulse is applied to the cells in the block. After completion of the previous steps, the memory elements are checked to determine if they still contain the appropriate data. At this point the erase operation is completed.
As is apparent, even a general description of a complete erase operation is quite complicated. When designing a flash memory system, the designer is often not aware of all the problems that may be present when the part is manufactured. These problems can result from the manufacturing process or be due to operational constraints that were not apparent during the design stage. As a result, the internal state machine that controls the operation of the memory system is purposely made to be very complex. After fabrication of the memory system, the system is cycled through its operations to determine whether the sequence of operations and sub-operations can be further optimized. If it is shown that the operation of the memory system is not optimal for its intended use, the circuit design is modified to improve its performance.
Modification of the memory system is usually carried out by re-designing and re-fabricating the part. As a typical memory system can contain thousands of logic gates, this process is both time consuming and expensive. In addition, most memory system designs do not permit an evaluation of how each step in the flow of the system's operation affects the other steps. This information can be useful in determining how a variation of one process step or parameter impacts the overall performance of the memory system.
What is desired is a memory system whose performance can be optimized without the necessity of re-designing and re-manufacturing the system. It is also desired to have a means for evaluating the impact of each step in the system's operation on the other steps so that the overall performance of the memory system can be improved. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.